This invention relates to a semiconductor integrated circuit (SIC) apparatus formed of self-aligned, high-speed bipolar transistors, and CMOS transistors inseparably associated on a single body of semiconductor material, and to an associated fabrication method.
In recent years, mobile communication tools such as mobile telephones have made remarkable advances, and techniques capable of integration of high-frequency circuits and high-integration logic circuits in a single SIC are required. In other words, a technique is required which is capable of inextricably binding self-aligned, high-speed bipolar transistors suitable for, for example, high-speed ECL (emitter-coupled logic) circuits, and high-integration, low-power CMOS logic circuits, on a single semiconductor substrate.
There are various self-alignment techniques. For example, Japanese Patent Application, published under Pub. No. 63-281456, shows a self-alignment technique. In accordance with this technique, a transistor with a self-aligned base extraction electrode and a self-aligned emitter extraction portion and a CMOS transistor are placed on a single semiconductor substrate.
FIG. 8 is a cross section of an SIC apparatus made in accordance in a conventional self-alignment technique. 54 is a p-type semiconductor substrate of silicon. Formed on the silicon substrate 54 are three transistors of different types, i.e., an npn bipolar transistor 51, a p-channel MOS (PMOS) transistor 52, and an n-channel MOS (NMOS) transistor 53. 57 is a first well region of p-type which is formed as follows. An epitaxial layer of an n-type semiconductor material is deposited all over the substrate 54. Subsequently, a region for isolation between devices of the epitaxial layer is subjected to an ion implant step and to a thermal annealing step, whereupon the p-well region 57 is formed such that it extends down to the silicon substrate 54. 59 is a LOCOS (local oxidation of silicon) layer for isolation between devices. The npn bipolar transistor 51, the PMOS transistor 52, and the NMOS transistor 53 are described in detail by making reference to FIG. 8.
The structure of the bipolar transistor 51 is now explained. 55A is an n-type buried collector region that is formed in the substrate 54 by means of ion implant and thermal annealing. 56A is an n-type collector region formed by subjecting the n-type epitaxial layer deposited over the entirety of the substrate 54, to an ion implant step and to a thermal annealing step. 61 is an emitter-base formation region formed in a self-aligned manner. 62A is a base extraction electrode for the bipolar transistor 51 of polycrystalline silicon (polysilicon) that is p-doped. 63A is an insulator layer of TEOS or the like material formed on top of the electrode 62A. 64A, 64B, 64C, and 64D are insulator side-wall layers for the electrode 62A composed of TEOS or the like material. 65 is an emitter extraction opening that is formed in a manner of self-alignment with the side-walls layers 64B and 64C. 66 is an emitter extraction electrode formed of polysilicon that is n-doped. 67 is a collector extraction electrode formed of polysilicon doped to n-type. 68 is a graft base region doped with impurities by a thermal annealing step through the electrode 62A. 69 is an active base region formed by a thermal annealing step. 70 is an emitter region formed, by a thermal annealing step performed through the electrode 66, in a manner of self-alignment with the side-wall layers 64B and 64C. 71 is a collector contact region formed by a thermal annealing step.
The structure of the PMOS transistor 52 is now explained. 55B is an n-type buried well region formed in the substrate 54 by an ion implant step. 56B is an n-type well region formed in the epitaxial layer. 60A is a first gate insulator layer formed by oxidation of a surface portion of the epitaxial layer. 62C is a first gate electrode formed of polysilicon doped to n-type. 63C is an insulator layer of TEOS or the like material formed on top of the electrode 62C. 64E is an insulator side-wall layer of TEOS or the like material for the electrode 62C. 72A is a first LDD (lightly doped drain) region that is formed in a manner of self-alignment with a side-surface of the electrode 62C. 73A is a first source-drain region that is formed in a manner of self-alignment with the side-wall layer 64E by means of an ion implant step.
The structure of the NMOS transistor 53 is now explained. 58 is a second p-type well region formed in the epitaxial layer in such a way as to extend to the substrate 54. 60B is a second gate insulator layer formed by oxidation of a surface portion of the epitaxial layer. 62D is a second gate electrode formed of polysilicon doped to n-type. 63D is an insulator layer of TEOS or the like material formed on top of the electrode 62D. 64G is an insulator side-wall layer for the electrode 62D. 72C is a second LDD region that is formed in a manner of self-alignment with a side-surface of the electrode 62D. 73C is a second source-drain region that is formed in a manner of self-alignment with the side-wall layer 64G by means of an ion implant step.
For example, in the PMOS transistor 52, the side-surface of the electrode 62C and the side-wall layer 64E act as a side-wall in order that an LDD structure, which is capable of suppressing generation of hot carriers which causes deterioration in performance, is achieved.
In the bipolar transistor 51, the side-wall layers 64B and 64C are formed and self-aligned in the same fabrication step as the side-wall layer 64E. As a result of such arrangement, the dimensions of the emitter region 70 are reduced thereby reducing junction capacitance. The distance between the electrode 62A and the emitter region 70 is made short to reduce base resistance. The high-frequency characteristics are improved.
The distance between the graft base region 68 and the emitter region 70 (hereinafter called the FIRST PARAMETER) is a key factor for both the value of base resistance and the carrier transit time affecting the way in which the bipolar transistor 51 operates. For example, the distance between the electrode 62C and the source-drain region 73A (hereinafter called the SECOND PARAMETER) is a key factor for both the resistance to hot carriers and the saturation drain current value affecting the way in which the PMOS transistor 52 operates.
The above-described SIC apparatus, however, has some disadvantages. For example, FIRST and SECOND PARAMETERS are determined by the thickness of the side-wall layer 64B and the thickness of the side-wall layer 64E. It is extremely difficult to determine both the thickness of the side-wall layer 64B and the thickness of the side-wall layer 64E in a single fabrication step for optimization of operating characteristics. Conventionally, in order to guarantee the performance of the PMOS transistor 52, the side-wall layer 64E which determines an LDD structure tends to be optimized in preference to the side-wall layer 64B. Therefore, it is difficult to secure a sufficient fabrication processing margin.
Further, in the bipolar transistor 51, the thick side-wall layers 64B and 64C are formed around the perimeter of the emitter-base junction. As a result, when the side-wall layers 64B, 64C, the thermal capacity of which is great, cool down, resulting contraction stress is applied to the perimeter of the emitter-base junction. This causes a deterioration in emitter-base leakage characteristic. Additionally, when the emitter width becomes narrow because of the miniaturization, the aspect ratio of the opening 65 (the ratio of the opening's 65 height to its diameter) increases. This results in increase in the emitter resistance.